This invention relates generally to output buffer circuits and more particularly, it relates to an improved output buffer arrangement for reducing induced chip noise at low temperature, high power supply voltage without degrading substantially its high operational speed.
In present day technology, digital logic circuits are widely used in the electronics field. One such use is for the interfacing between the logic of one integrated circuit device and another integrated circuit device. An output buffer circuit is an important component for this interface function. The output buffer provides, when enabled, an output signal which is a function of a data input signal received from other logic circuitry of the integrated circuit.
One of the problems associated with such output buffer circuits is their generation of power supply noise due to very fast switching speed. There have been attempts made in the prior art to relieve or solve the noise problem by a general slowing down of the output stage transistors in the output buffers. However, these solutions have the disadvantage of causing speed deterioration at slow bias conditions (i.e., low power supply voltage, hot temperatures, and slow process corners).
It would therefore be desirable to provide an improved output buffer arrangement for reducing induced chip noise at fast bias conditions comparable to conventional output buffer circuits but yet retains high operational speeds at slow bias conditions. The output buffer arrangement of the present invention provides a P-channel gate bias potential, which varies favorably with temperature, power supply voltage and process so as to yield well-controlled current sources, for controlling the switching speed of the output stage transistors in order to limit excessive noise.